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| November 2002 CT RO DU NT LETE P EPLACEME at O BS O DE D R nter EN rt Ce /tsc COMM S upp o NO RE r Technical .intersil.com ww t ou contac TERSIL or w N 1-888-I (R) CD22301 Monolithic PCM Repeater Features * Automatic Line Buildout * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1V * Buffered Output Description The CD22301 monolithic PCM repeater circuit is designed for T1 carrier systems operating with a bipolar pulse train of 1.544Mbits/s. It can also be used in the T148 carrier system operating with a ternary pulse train of 2.37Mbits/s. The circuit operates from a 5.1V 5% externally regulated supply. The CD22301 provides active circuitry to perform all functions of signal equalization and amplification, automatic line buildout (ALBO), threshold detection, clock extraction, pulse timing and buffered output formation. Applications * Bipolar Carrier System . . . . . . . . . . . . . T1 1.544Mbits/s * Ternary Carrier System . . . . . . . . . . . . T148 2.37Mbits/s Part Number Information PART NUMBER CD22301E TEMP. RANGE (oC) -40 to 85 Pinout PACKAGE 18 Ld PDIP PKG. NO. E18.3 ALBO GROUND ALBO 1 OUTPUT ALBO 2 OUTPUT ALBO 3 OUTPUT PREAMP INPUT + PREAMP INPUT PREAMP OUTPUT + PREAMP OUTPUT VEE 1 2 3 4 5 6 7 8 9 18 SUBSTRATE 17 ALBO BIAS 16 OSC BIAS 15 LC TANK INPUT 14 VCC 13 CLOCK LIMITER OUTPUT 12 TIMING PULSE INPUT 11 OUTPUT PULSE 1 10 OUTPUT PULSE 2 CD22301 (PDIP) TOP VIEW Functional Diagram ALBO OUTPUT CIRCUIT ALBO GND 1 ALBO BIAS 17 1K VCC 15K 100 100 100 50K 18K FROM ALBO PEAK DETECTOR AO1 AO2 2 3 100 100 100 VEE AO3 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1 All other trademarks mentioned are the property of their respective owners. FN1368.4 CD22301 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Input Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . . 25mA Peak Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . 100mA Input Surge Voltage (Between Pins 5 and 6, t = 10ms) . . . . . . . 50V Output Surge Voltage (Between Pins 10 and 11, t = 1ms). . . . . 50V Power Dissipation For TA = -40oC to 60oC. . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW For TA = 60oC to 85oC . . . . Derate Linearly 12mW/oC to 200mW Device Dissipation per Output Transistor For TA = Full Package Temperature Range (All Types) . . . . 100mW Thermal Information Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40oC TA 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TA = 25oC, VCC = 5.1V 5% (See Figure 4) PARAMETER MIN TYP MAX UNITS STATIC DC VOLTAGES ALBO Pins (Pins 2, 3, 4 and 17) Pre Amp Inputs and Outputs (Pins 5, 6, 7 and 8) Output Pulse 1, 2 (Pins 10 and 11) Oscillator/Clock (Pins 12, 13, 15 and 16) STATIC DC CURRENTS ICC Output Pulse 1, 2 (Pins 10 and 11) 22 0 30 100 mA A 2.4 3.1 0 2.9 5.1 3.6 0.1 3.4 4.1 V V V V Electrical Specifications PARAMETER DYNAMIC SPECIFICATIONS Preamplifier Input Impedance Preamplifier Output Impedance Preamplifier Gain at 2.37MHz Preamplifier Output Offset Voltage Clock Limiter Input Impedance ALBO Off Impedance ALBO On Impedance DATA Threshold Voltage CLOCK Threshold Voltage ALBO Threshold VTH(D) as % of VTH(AL) VTH(CL) as % of VTH(AL) Buffer Gate Voltage (low) Differential Buffer Gate Voltage Output Pulse Rise Time TA = 25oC, VCC = 5.1V 5% SYMBOL FIGURE NOTE MIN TYP MAX UNITS ZIN ZOUT AO VOUT ZIN(CL) ZALBO(off) ZALBO(on) VTH(D) VTH(CL) VTH(AL) 7 7 7 7 5 5 5 6 6 6 1 2 3 4 5, 8 6, 8 7, 8 20 47 -50 10 20 0.62 0.92 1.4 44 66 50 0 0.7 1.1 1.5 47 73 0.8 0 - 2 50 10 0.78 1.28 1.6 49 80 0.95 0.15 40 k k dB mV k k V V V % % V V ns VOL VOL tR 4 4 4, 8 9 9 9, 10 0.65 -0.15 - 2 CD22301 Electrical Specifications PARAMETER Output Pulse Fall Time Output Pulse Width Pulse Width Differential Clock Drive Current NOTES: 1. No signal input. Measure voltage between pins 7 and 8. 2. Measure clock limiter input impedance at pin 15. See Figure 5. 3. Adjust potentiometer for 0V (See Figure 5). Measure ALBO off impedances from pins 2, 3 and 4 to pin 1. 4. Increase potentiometer until voltage at pin 17 = 2V (See Figure 5). Measure ALBO on impedances from pins 2, 3 and 4 to pin 1. 5. Adjust potentiometer for V = 0V (See Figure 6). Then slowly increase V in the positive direction until pulses are observed at the DATA terminal. 6. Continue increasing V until the DC level at the clock terminal drops to 4V (See Figure 6). 7. Continue increasing V until the ALBO terminal rises to 1V (See Figure 6). 8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6 and 7. 9. Set eIN = 2.75mVRMS at f 1.185MHz. Adjust frequency until maximum amplitude is obtained at pin 15. Observe output pulses at pins 10 and 11. 10. Adjust input signal amplitude until pulses just appear in outputs. Increase input amplitude by 3dB. TA = 25oC, VCC = 5.1V 5% (Continued) SYMBOL tF tW tW ICL FIGURE 4, 8 4, 8 4, 8 NOTE 9, 10 9, 10 9, 10 MIN 290 -10 TYP 324 0 2 MAX 40 340 10 UNITS ns ns ns mA + 1F SUBSTRATE ALBO ALBO 18 BIAS 17 GND 1 0.1 F ALBO OUTPUT CIRCUIT SEE FIG. 1 17H 600 - 800pF 120K BIAS LC TANK 16 15 INPUT 14 VCC AO1 2 AO2 3 4 AO3 0.1F 2200pF 470H 2.7K 8.2K 1500pF 1.8K PULSE INPUT 430 0.1F 15H 510 82pF 5 150pF 6 130 1.33K 4.53K 0.1F 6.19K 7 8 PEAK DETECTOR CLOCK CIRCUIT SEE FIG. 2 LIMITER TIMING PULSE AMPLIFIER 13 PREAMPLIFIER CLOCK THRESHOLD COMPARATOR 12 100 H PHASE SHIFT NETWORK 3.83K 33pF DATA THRESHOLD COMPARATOR GATE FF 11 PULSE OUTPUT GATE FF 10 9 VEE VCC FIGURE 1. TYPICAL 1.544MHz T1 REPEATER SYSTEM 3 CD22301 16 15 VCC VCC VCC FROM LIMITER TO AMPLIFIER 5.1K 5.1K 5.5K 13 12 TO TIMING PULSE AMPLIFIER 12K VEE VEE VEE FROM CLOCK THRESHOLD DETECTOR FIGURE 2. CLOCK INTERFACE CIRCUIT FIGURE 3. PHASE-SHIFT INTERFACE CIRCUITS 1 2 3 0.1F eIN 0.001 F 8.2k 8.2k 0.1 F 4 5 6 7 8 9 18 1F 17 16 L1 (NOTE) 15 14 3.83k 13 12 130 11 10 20 pF 100H C1 (NOTE) 91k VCC = 5.1V 0.1F 0.68F NOTE: C1 AND L1 RESONATE AT 1.272MHz 130 PULSE OUTPUT FIGURE 4. DC AND OUTPUT PULSE TEST CIRCUIT 1 2 3 4 5 6 7 8 9 18 17 16 15 14 0.01F 13 12 11 10 VCC = 5.1V 0.1F 5K FIGURE 5. TEST CIRCUIT FOR IMPEDANCE MEASUREMENT 4 CD22301 1 2 3 4 5 6 7 8 9 5k V 18 1F 17 1F 16 15 1F 2k VCC = 5.1V 14 1F 13 0.1F 75 12 IN4152 11 10 130 2.75VRMS at 1.185MHz CLOCK - 3V + 8.2k 8.2 k 0.1 F 0.1 F 0.1 F 8.2k 8.2k 0.1 F DATA FIGURE 6. TEST CIRCUIT FOR THRESHOLD VOLTAGE MEASUREMENT 1 2 NC 3 4 1.0F ein 5 6 50 200 k 1.0 F 200k 7 8 9 18 17 16 15 14 0.1F 13 12 11 10 VCC = 5.1V NC NC FIGURE 7. PREAMPLIFIER GAIN AND IMPEDANCE MEASUREMENT CIRCUIT 100% 90% tW 50% 0% 10% tR tF FIGURE 8. OUTPUT PULSE WAVEFORM 5 |
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